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TECH GM SYSTEM'S WEBSITE WAS SELECTED BY TECH EDGE AS A COOL TECH WEBSITE

2/7/2016

JANUARY 4, 2016 GM SYSTEM'S WEBSITE HAS BEEN SELECTED BY
TECH3EDGE AS ONE OF THE "COOL AND INTERESTING WEBSITES ON ELECTRONICS TECHNOLOGY IN THE U.S."
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"IT WAS NICE GETTING AN ACCOLADE FOR OUR WEB SITE AND WE WILL CONTINUE TO BREAK NEW GROUND."

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Let Your Fan Out: Boo-yahTom Terlizzi, VP, GM Systems,

2/4/2016

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FIGURE 2

Just in time for the Super Bowl and like the “Stub Hub” commercial below, in Figure 1 (VIDEO), above “You can’t have your Fan-out in here”. So what’s all this hype on Fan-out Wafer Level Packaging (FO-WLP)?
“Let your Fan out:Boo-Yah1"

FAN IN WLP
First, let us define Fan-In WLP.
Fan In WLP means the flip chip interconnects are within the outline of the die as shown in Figure 2. Typically, integrated circuit die have peripheral I/O bonding pads, which are routed to a “X-Y” grid in rows and columns as shown in Figure 2 above. This is accomplished by adding another thin film conductor layer over a polyimide passivation called a redistribution layer (RDL).

“Fan-In WLP"

Figure 3
Infineon Fan out wafer Process (eWLP)1,2 as shown in Figure 3

Fan Out WLP means that the flip chip interconnects extend outside the outline of the example 3 mm die as shown in Figure 4. By extending the connections outside the die outline, a reduced I/O pitch is obtained.

FIGURE 4

Why Fan out WLP?1

WHY IS FAN OUT WLP SO IMPORTANT2,3?

Eliminates die interconnect (bumps and wire bonds) and substrate

Excellent Electrical Performance – Shorter interconnects = Lower parasitic
Eliminate interconnect stress and ELK (extreme low dielectric constant) crack delamination issues
Fine Line/Space (L/S) for better RDL “route-ability”
Finer pad pitch on die than flip chip
Thin package, Smaller Form Factor, Potential System in Package (SiP), Multi-die, 3D Solutions
– High integration – Heterogeneous chips including passives and /or Integrated Passive Devices (IPD)

With die size reduction and higher pin count manufacturers will have two options:

Reducing ball pitch in order to have more connections within the die surface Going Fan-Out and allowing an easier redistribution
Since pitch reduction is very challenging, Fan-Out approach is offering a good compromise on next level (board) surface mount technology (SMT)

Conclusion:
Dan Tracy, SEMI, stated, “packaging is a key enabler of functionality in the mobile space ─ due to thin, small form factor multi-die and SiP applications growing. He also stressed that Fan-out wafer-level packaging (FO-WLP) is disruptive and will have a significant impact on the consumption of semiconductor packaging materials in the coming years.”
References

“Overview of Fan-out Wafer Level Package (FO WLP) and Fan -out Panel Level Package (FO-PLP)”, Charlie Lu, Altera
“Introduction to Fan-Out Wafer Level Packaging” Beth Keser, Qualcomm
Introduction to Advanced Microelectronic Packaging Technologies Course/Training, TJ Green Associates LLC. See description below

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Authors

Principal author is Tom Terlizzi VP at GM Systems a Management and Technology consulting firm, providing Business & Strategic plans, Acquisitions, Marketing & Sales strategy, Product development for electronics, microelectronic and proposal support. Various guest author on technology, sales, management and manufacturing topics are also presented. Additional topics political or special interest in nature may be added

TECH GM SYSTEM'S WEBSITE WAS SELECTED BY TECH EDGE AS A COOL TECH WEBSITE

Let Your Fan Out: Boo-yahTom Terlizzi, VP, GM Systems,

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